HyperTransport
- HTX redirects here. For the Danish examination programme, see Higher Technical Examination Programme (HTX)
HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency computer bus that was introduced on April 2nd of 2001[1]. The HyperTransport Technology Consortium is in charge of promoting and developing HyperTransport technology. The technology is used by AMD and Transmeta in x86 processors, PMC-Sierra, Broadcom, and Raza Microelectronics in MIPS microprocessors, ATI Technologies, NVIDIA, VIA, SiS, ULi/ALi, AMD, Apple Computer and HP in PC chipsets, HP, Sun Microsystems, IBM, and IWill in servers, Cray, Newisys, and PathScale in high performance computing, and Cisco Systems in routers. Notably missing from this list is semiconductor giant Intel, which continues to use a shared bus architecture.
Overview
HyperTransport comes in three versions — 1.0, 2.0, and 3.0 — which run from 200MHz to 2.6GHz (compared to PCI at either 33 or 66 MHz). It is also a DDR or "Double Data Rate" bus, meaning it sends data on both the rising and falling edges of the clock signal. This allows for a maximum data rate of 5200 MTransfers/s per pair running at 2.6GHz; this frequency is auto-negotiated.
HyperTransport supports an auto-negotiated bus width, based on two 2-bit lines to 32-bit lines. The full-sized, full-speed, 32-bit bus in each direction has a transfer rate of 20,800 MByte/s (2*(32/8)*2600), making it much faster than many existing standards. Buses of various widths can be mixed together into a single application (for example, 2x8 instead of 1x16), which allows for higher speed buses between main memory and the CPU, and lower speed buses among peripherals as appropriate. The technology also has much lower latency than other solutions.
HyperTransport is packet-based, with each packet always consisting of a set of 32-bit words, regardless of the physical width of the bus interconnect. The first word in a packet is always a command word. If a packet contains an address, then the last 8 bits of the command word are chained with the next 32-bit word in order to make a 40-bit address. An additional 32-bit control packet is allowed to be prepended when 64-bit addressing is required. The remaining 32-bit words in a packet are the data payload. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.
HyperTransport packets enter the bus in segments known as bit times. The number of bit times that it necessitates depends on the width of the bus. HyperTransport can be used for generating system management messages, signaling interrupts, issuing probes to adjacent devices or processors, and general I/O and data transactions. There are usually two different kinds of write commands that can be used - posted and non-posted. Posted writes are ones that do not require a response from the target. This is usually used for high bandwidth devices such as UMA traffic or DMA transfers. Non-posted writes require a response from the receiver in the form of a "target done". Reads also cause the receiver to generate a read response.
HyperTransport also greatly facilitates power management as it is ACPI compliant. This means that changes processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep.
Electrically, HyperTransport/LDT is similar to Low Voltage Differential Signaling (LVDS) operating at 2.5V.
There has been marketing confusion between the use of HT referring to HyperTransport and the use of HT to refer to Intel's Hyper-Threading feature of their Pentium 4 based microprocessors. Hyper-Threading is known as Hyper-Threading Technology (HTT) or HT-Technology. Because of this potential for confusion, the HyperTransport Consortium always uses the written out form: "HyperTransport".
Applications for HyperTransport
Front-Side Bus Replacement
The primary use for HyperTransport is to replace the front-side bus, which is currently different for every machine (or some set of them). For instance, a Pentium cannot be plugged into a PCI bus. In order to expand the system the front-side bus must connect through adaptors for the various standard buses, like AGP or PCI. These are typically included in the respective controller functions, namely the northbridge and southbridge.
A similar computer implemented with HyperTransport is more flexible, as well as being faster. A single PCI<->HyperTransport adaptor chip will work with any HyperTransport enabled microprocessor and allow the use of PCI cards with these processors. For example, the NVIDIA nForce chipset uses HyperTransport to connect its north and south bridges.
Multiprocessor interconnect
Another use for HyperTransport is as an interconnect for NUMA multiprocessor computers. AMD uses HyperTransport with a proprietary cache coherency extension as part of their Direct Connect Architecture in their Opteron and Athlon64 line of processors. The HORUS interconnect from Newisys extends this concept to larger clusters.
Router or Switch Bus Replacement
HyperTransport can also be used as a bus in routers and switches. Routers and switches have multiple connections ports and data has to be forwarded between these ports as fast as possible. E.g. a four port 100 MBit/s Ethernet router needs a bus that is 800 MBit/s fast (100 MBit/s * 4 ports * 2 directions). HyperTransport greatly exceeds the bandwidth needed for this application.
HTX and Co-processor interconnect
The issue of bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. After years without an officially recognized one, a connector designed for such expansion using a HyperTransport interface was recently introduced and is known as HyperTransport eXpansion (HTX). Using the same mechanical connector as a 16-lane PCI-Express slot, HTX allows plug-in cards to be developed which support direct access to a CPU and DMA access to the system RAM. Recently, co-processors such as FPGAs have appeared which can access the HyperTransport bus and become first-class citizens on the motherboard. Current generation FPGAs from both of the main manufacturers (Altera and Xilinx) can directly support the HyperTransport interface and have IP Cores available.
Unfortunately, the existing HTX specification allows Hypertransport devices attached through HTX connectors to communicate at only a quarter of Hypertransport's full throughput, as it uses PCI-E's 16-bit connector and is downclocked to a mere 1.4Ghz in spite of an earlier Samtec connector[2] supporting 32-bit, 2.8Ghz operation.
Implementations
- AMD AMD64 and DirectConnect based Central Processing Units.
- ht_tunnel from OpenCores project (MPL licence)
- ATI Radeon® Xpress 200 for AMD Processor
- NVIDIA nForce™ Professional MCPs (media and communications processors)
- ServerWorks HT-2000 HyperTransport™ SystemI/O™ Controller
- Apple desktop computers featuring the PowerPC G5