Wired logic connection: Revision history

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curprev 00:4100:41, 18 September 2024‎ Wtshymanski talk contribs‎ 5,198 bytes 0‎ These are non-inverting buffers. Schematics no longer explain the concept to someone not already in the know. Undid revision 1242541278 by 213.233.155.154 (talk) undo Tag: Undo

curprev 18:3018:30, 23 April 2024‎ BD2412 talk contribs‎ m 5,198 bytes −4‎ clean up spacing around commas and other punctuation fixes, replaced: ,P → , P undo Tag: AWB

curprev 15:0915:09, 20 April 2024‎ SaintSinner01 talk contribs‎ 5,202 bytes +65‎ #suggestededit-add-desc 1.0 undo Tags: Mobile edit Mobile app edit Android app edit

curprev 20:0120:01, 8 April 2023‎ PeterBFZ talk contribs‎ 5,137 bytes −1‎ The LOW, LOW cas was missing in a table. Corrected. undo

curprev 21:3921:39, 15 January 2023‎ Em3rgent0rdr talk contribs‎ 3,868 bytes −70‎ I made a circuitjs simulated gif for wired AND & OR diode logic, which cycle through all possible logic states & show current & voltages undo Tag: Visual edit
curprev 19:0419:04, 15 January 2023‎ Em3rgent0rdr talk contribs‎ 3,938 bytes +45‎ →‎Compatibility of wired AND OR using diodes: simplify wording "shifted positive or negative" => "reduced"..."to ground". And break sentence in two so can add clarification "Without amplification,..." undo Tag: Visual edit
curprev 01:0601:06, 15 January 2023‎ Em3rgent0rdr talk contribs‎ m 3,893 bytes −9‎ shorten my parenthetical a bit: "particularly more than CMOS" undo Tag: Visual edit
curprev 01:0301:03, 15 January 2023‎ Em3rgent0rdr talk contribs‎ 3,902 bytes +183‎ Change "Limitations are" to "Limitations include" because not necessarily exhaustive list of limitations, and added "constant ohmic heating for most logic (which is much higher than CMOS logic) which indirectly limits density of components and speed." (e.g. 3 out of 4 truth tables for AND and OR have constant current through the resistor, producing V^2/R power dissipation. undo Tag: Visual edit

curprev 11:0911:09, 9 November 2022‎ OookLout talk contribs‎ m 3,719 bytes +19‎ Clarified and simplified description of logic gate behaviour. undo Tag: Visual edit
curprev 04:0404:04, 9 November 2022‎ Wtshymanski talk contribs‎ 3,700 bytes −28‎ Wikipedia doesn't recommend and doesn't care if you die screaming undo

curprev 23:1223:12, 4 November 2022‎ 172.56.241.126 talk‎ 3,728 bytes −8‎ Change "likely" to "may". Using schottky diodes results in lower voltage drop and the resulting output will meet logic level requirements. undo

curprev 02:4202:42, 12 February 2022‎ Tanner Swett talk contribs‎ 3,655 bytes −11‎ Change "using only active and passive components" back to "using only passive components" undo

curprev 11:3211:32, 15 February 2021‎ PV-BC500 talk contribs‎ m 3,666 bytes 0‎ No edit summary undo
curprev 10:2810:28, 15 February 2021‎ PV-BC500 talk contribs‎ 3,666 bytes +66‎ Added "Open Collector AND gate" diagram undo

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